xilinx vivado 2020.1 and VMware Horizon Server
it is meant to provide an opportunity to improve the knowledge of the VHDL language and, more importantly, to design a digital “system”. You will be expected to learn to: a) implement digital system design in VHDL code; b) synthesise and download it to the target hardware;which would be simulated since there is no physical basys 3 fpga hardware. c) test, debug, and verify that the design meets the specifications; d) report about your design.
You are required to design code for your target hardware (a Digilent Basys3 board with a Xilinx Artix 7 FPGA) in order to implement a design that meets the specifications (below). Your design will be varied by testbenches in Vivado simulator. You are required to submit working and correct code and you are strongly encouraged to use a modular coding style (allowing for greater flexibility, maintainability, modularity, and reusability). To show that you master all aspects of the language, your code should prevalently use concurrent statements for combinatorial circuits and sequential code for sequential circuits. Additionally, the use of non-standard packages (e.g. STD_LOGIC_ARITH, STD_LOGIC_UNSIGNED, STD_LOGIC_SIGNED) and BUFFER ports is forbidden, while the use of INOUT ports is accepted only when strictly necessary.
You are supposed to gain familiarity with VHDL coding during the supporting CE869 lectures videos and through self-study hours, also with the help of the recommended textbooks or any other book about VHDL. You are expected to work on this assignment mostly during your own hours. Your design project should be stored under the revision control repository that was assigned to you at the beginning of the course. You are supposed to commit often and describe your progress in the commit messages. In order to promote a learning scheme that values the learning process in addition to the submitted final design, your weekly progress (as traced back by the commit logs) will contribute to your assignment mark.